Program D Flip - Flop Pada VHDL

VHDL Code untuk D Flip-Flop

library IEEE;
use IEEE.std_logic_1164.all;


entity d_ff_srss is
port (
d,clk,reset,set : in STD_LOGIC;
q : out STD_LOGIC);
end d_ff_srss;


architecture d_ff_srss of d_ff_srss is
begin
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
q <= '0';
elsif set='1' then
q <= '1';
else
q <= d;
end if;
end if;
end process;
end d_ff_srss;

                      
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